SAM Accelerator

CoCoVGA SAM Accelerator

The CoCoVGA SAM accelerator hardware plugs into the SAM chip socket and enables true double-speed functionality on a CoCo 1 or 2 when accessing both ROM and RAM. This hardware requires version 0.92 or later of the CoCoVGA FPGA. See also Ed Snider's page at https://thezippsterzone.com/2019/04/04/cocovga-sam-accelerator/.

The SAM (Synchronous Address Multiplexer - 6883/74LS783 or 74LS785), as used in the Color Computer 1 and 2, has the responsibility of:

  • Dividing the XTAL frequency to clock frequencies usable by the 6809 CPU and 6847 VDG (Video Display Generator)
  • Multiplexing CPU and VDG accesses to RAM and ROM
  • DRAM refresh

Given a 14.31818MHz input from a crystal, it provides 3 different clock frequency modes:

SAM CPU clocking mode

Comments

BASIC pokes to select mode

6809 CPU clock frequency

6847 VDG clock frequency

Slow /16

Default power-on/reset mode

POKE &HFFD8,1
POKE &HFFD6,1

or

POKE 65496,1
POKE 65494,1

0.89MHz

3.58MHz

Address Dependent /16 or /8

CPU clock frequency varies depending on whether access is to RAM (slow) or ROM (fast)

POKE &HFFD7,1

or

POKE 65495,1

0.89MHz or 1.78MHz

3.58MHz

Fast /8

DRAM refresh and multiplexing with VDG non-operational, resulting in scrambled video display

POKE &HFFD9,1

or

POKE 65497,1

1.78MHz

3.58MHz

The CoCoVGA SAM accelerator resolves the downsides of the “Fast” mode described in the table above by intercepting the clocking mode register writes and instead of allowing the SAM to alter its clock divider and muxing, it doubles the crystal input frequency to the SAM. The SAM continues to mux between the CPU and VDG normally and perform DRAM refresh as it would in “Slow” mode.

This also means that from a user’s perspective there is no longer any difference between the “Address Dependent” and “Fast” modes, other than the 6847 VDG’s doubled horizontal and vertical sync interrupt rate.

SAM CPU clocking mode

Comments

BASIC pokes to select mode

6809 CPU clock frequency

6847 VDG clock frequency

Slow /16

Default power-on/reset mode

POKE &HFFD8,1
POKE &HFFD6,1

or

POKE 65496,1
POKE 65494,1

0.89MHz

3.58MHz

Slow /16 but with double- frequency input clock

Clock input to SAM is doubled from 14.31818MHz to 28.63636MHz

POKE &HFFD7,1

or

POKE &HFFD9,1

or

POKE 65495,1

or

POKE 65497,1

1.78MHz

7.16MHz

As alluded to earlier, note that the VDG clock frequency is also doubled in the table above. Normally, this would result in loss of video - that is, the connected TV or monitor would no longer be able to sync at this frequency. Because CoCoVGA has its own crystal for driving VGA output and because it buffers entire frames of video, it can still properly display the video with a 60Hz VGA-spec refresh rate despite the now nearly 120Hz field sync rate of the 6847 VDG.

This upgrade requires DRAM which is capable of 150ns (or faster) operation and may also need 2MHz PIAs.

This enhancement was designed and manufactured by Ed Snider with CoCoVGA FPGA support from Brendan Donahe.

Resources: